The present invention relates to a nonvolatile semiconductor storage device for writing parallel multi-value data into a plurality of memory cells.
The nonvolatile semiconductor storage devices have made a remarkable progress in recent years, and their storage capacities are rapidly increasing. Accordingly, as a method for increasing the storage capacity through the same manufacturing processes as those of the prior art, there is the method of increasing the number of bits of information that can be stored in one memory cell (i.e., providing the so-called multi-value structure). In this multi-value nonvolatile semiconductor storage device, the threshold voltage of each memory cell is controlled. In the above nonvolatile semiconductor storage device, four values (two bits per cell in terms of the amount of information) are stored into one memory cell, and the values are made to be "0, 0", "0, 1", "1, 0" and "1, 1" in descending order of the threshold voltage of the memory cell. Assuming that the data "0, 0" represents an erased state, then a write operation is executed by shifting the threshold voltage of the memory cell in this erased state to the lower threshold voltages in order of the data "0, 1", "1, 0" and "1, 1". Although there is also a nonvolatile semiconductor storage device wherein the threshold voltage of the memory cell from which data has been erased is lower than the threshold voltage of the memory cell into which data has been written, it is essentially the same.
As a nonvolatile semiconductor storage device for writing such multi-value data, there has been proposed one which independently operates a write operation and a verify operation in the order of, for example, "0, 1", "1, 0" and "1, 1" ("A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications" ISSCC96 DIGEST OF TECHNICAL PAPERS P32-P33).
However, the above nonvolatile semiconductor storage device has the following problems (1) through (4).
(1) Since the verify operation is executed every multi-value data, the time necessary for this verify operation is prolonged to be about three times that in the case of binary value when, for example, four-value data is stored into one memory cell.
(2) Since a word line voltage at the time of the write and verify operations must be varied in accordance with the threshold voltage of the multi-value data to be verified, a time for varying the word line voltage is necessary.
(3) Since the voltage applied to the bit line is constant regardless of the value of the multi-value data in the write stage and a voltage that ranges from a negative voltage of a small absolute value for the data "0, 1" to a negative voltage of a large absolute value for the data "1, 1" is applied to the word line, many write pulses are necessary.
(4) There is caused gate disturbance of the memory cells commonly connected to an identical word line.